TU Delft research suggests back contact tech may push crystalline silicon PV over 28% threshold
A research group led by Delft University of Technology (TU Delft) in the Netherlands has conducted a series of electrical simulations to assess the potential of carrier-selective contacts (CSCs) to achieve higher efficiencies in crystalline silicon (c-Si) solar cells and have found that their use in front/back-contacted (FBC) and interdigitated back-contacted (IBC) designs may help break the 28% threshold.
“Our expertise in accurate and advanced simulations is at the core of this visionary approach to unlock the full potential of Carrier-Selective Contacts in c-Si solar cells,” said the research's corresponding author, Paul Procel. “We bridge theoretical and practical knowledge, driving design innovations, and identifying key bottlenecks that limit the theoretical efficiency of FBC and IBC solar cells. This powerful methodology extends beyond c-Si solar cells and is applicable to tandem solar cells and other electronic devices.
Research co-author Yifeng Zhao explained that advancements in patterning technology are crucial for achieving record efficiency in c-Si solar cells, enabling narrower lines and localized contacts in FBC and IBC architectures. “With simulation guidance, we have experimentally demonstrated high-efficiency localized FBC-SHJ solar cells, highlighting the key role of patterning advancements in further boosting SHJ solar cell performance,” he added.
In the paper “,” published in Solar Energy Materials and Solar Cells, the research team identified three interdependent critical factors showing why CSCs will be a crucial component to achieve higher efficiency and said these factors can be “rigorously assessed” by solving the Poisson equation, which is an elliptic partial differential equation used in theoretical physics.
The first factor is the difference in work function between the substrate and the deposited material. Future research, the researchers said, will have to help determine when CSCs work better as an electron contact by an electron transport layer (ETL) or a hole contact by a hole transport layer (HTL). This would establish the electric field in the absorber bulk, with a lower work function in the deposited layer designating the ETL and the higher defining the HTL.
The second key factor is represented by energy barriers at the absorber bulk interface, which refer to energy alignment between occupied and available energy states at both sides of the barrier and effectively hinder the transport of unwanted charge carriers and enhance the functionality of CSCs.
Key to the barriers' creation are the energy band offset, the Fermi level and the thickness of deposited layers. “We refer to energy level and width of the energy barrier as high/low and thick/thin, respectively,” the researchers stated. “For instance, efficient charge collection occurs when the energy barriers in the conduction or valence bands are low and thin, allowing efficient transport of electrons or holes in the n- or p-contact, respectively. Since CSCs are designed to selectively collect only one type of charge carrier, it is desirable to have high and thick barriers in the valence or conduction bands at the n- or p-contacts, respectively.”
When it comes to the third factor, the group said energy states are crucial for the collection of charge on the other side of the energy barrier, noting that the energy states at the bulk interface are mostly occupied by collecting carriers.
The simulations framework considered different heterojunction (HJT) and TOPCon solar cell architectures based on several CSC designs, including poly-silicon (poly-Si) and dopant-free structures. It also took into account metallization pitch, c-Si thickness, and wafer resistivity, with some of the analyzed cell designs being based on transparent conductive oxide (TCO) or being dopants-free.
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